The disclosure relates to a nonvolatile memory device and a method of programming the same.
A nonvolatile memory device has various advantages. For example, it can allow random access to the memory, enable data writing and erasure, permit read only access to the memory, retain data even without the supply of power, etc. Therefore, nonvolatile memory devices have recently been widely used as/in the storage media for portable electronic devices, such as digital cameras, personal digital assistants (PDAs), and MP3 players.
FIG. 1A is a diagram showing a nonvolatile memory device 100.
Referring to FIG. 1A, the nonvolatile memory device 100 includes a memory cell array 110, a page buffer unit 120, and a control unit 130.
The memory cell array 110 includes a plurality of memory blocks. Each of the memory blocks includes a plurality of memory cells. The memory cells are coupled to respective bit lines BL and word lines WL.
The page buffer unit 120 includes page buffers PB each coupled to one or more of the bit lines BL. The page buffer unit 120 outputs a verification signal through a verification line nWDo coupled in common to the page buffers PB.
The control unit 130 outputs a control signal to control the operations of the nonvolatile memory device 100 and determines a program pass or a program fail on the basis of the verification signal. The control unit 130 includes an error correcting code (ECC) circuit 131 for error correction.
The ECC circuit 131 performs error correction for a specific number or more of fail bits when a program verification operation is performed or when data is read.
The nonvolatile memory device 100 can perform an intelligent verification operation using the ECC circuit 131. In the intelligent verification operation, when the number of fail bits is within a correctable number during program verification, a corresponding program operation is no longer performed. According to the intelligent verification operation, the time that it takes to perform a program operation can be reduced.
The page buffer PB of the nonvolatile memory device 100 is described in more detail below.
FIG. 1B is a detailed diagram of the page buffer PB shown in FIG. 1A.
Referring to FIG. 1B, the memory cell array 110 includes a number of the memory blocks BK0 to BKn. Each of the memory blocks includes a plurality of cell strings CS. Each of the cell strings CS is coupled to an even bit line BLE or an odd bit line BLO.
The cell string CS includes first to thirty-second memory cells C0 to C31 coupled in series between a drain select transistor DST and a source select transistor SST.
To the gate of the drain select transistor DST is coupled a drain selection line DSL. To the gate of the source select transistor SST is coupled a source selection line SSL.
First to thirty-second word lines WL0 to WL31 are coupled to the respective gates of the first to thirty-second memory cells C0 to C31.
The nonvolatile memory device 100 performs a program on a page basis. In a single level cell (SLC) memory where each cell is capable of storing one bit, one page corresponds to one word line.
In a multi-level cell (MLC) memory where each cell is capable of storing 2 bits or more, one word line corresponds to a physical page that can include a plurality of logical pages depending on the number of bits that can be stored in each cell. For example, in a multi-level cell (MLC) memory where each cell is capable of storing 3 bits, one physical page includes three logical pages.
The even bit line BLE or the odd bit line BLO is coupled to the drain of the drain select transistor DST. A common source line SL is coupled to the source of the source select transistor SST.
Meanwhile, the page buffer unit 120 includes the page buffers PB each coupled to one or more of the bit lines BL. Each of the page buffers PB includes a bit line selection unit 121, a detection unit 122, a precharge unit 123, a cache latch L1, and a main latch L2.
The bit line selection unit 121 selects one of the even bit line BLE and the odd bit line BLO and couples the selected bit line BLE or BLO to a first detection node SO1. The detection unit 122 detects a voltage of the selected bit line BLE or BLO coupled to the first detection node SO1 and changes a voltage of a second detection node SO2 on the basis of the detected voltage.
The precharge unit 123 precharges the second detection node SO2. The cache latch L1 and the main latch L2 either (i) latch data according to the voltage of the second detection node SO2 or (ii) latch data to be programmed and then output the latched data to the second detection node SO2.
The cache latch L1 is coupled to a data input and output (I/O) line IO. The cache latch L1 inputs or outputs data to or from the data I/O line and stores data during a cache program operation. The main latch L2 is used to program data transferred by the cache latch L1.
In a program verification operation, a verification result stored in the main latch L2 is moved to the cache latch L1, and the program verification operation is performed through the verification line nWDo coupled to the cache latch L1. The page buffer PB can further includes a temporary latch (not shown) for storing data.
The bit line selection unit 121 includes first to fourth NMOS transistors N1 to N4. The detection unit 122 includes a fifth NMOS transistor N5. The precharge unit 123 includes a PMOS transistor P. The latch unit 124 includes one or more latch circuits.
The first and second NMOS transistors N1, N2 are coupled between the even bit line BLE and the odd bit line BLO. A variable voltage VIRPWR is supplied to a node between the first and second NMOS transistors N1, N2.
An even discharge control signal DISCHE is supplied to the gate of the first NMOS transistor N1. An odd discharge control signal DISCHO is supplied to the gate of the second NMOS transistor N2.
The third NMOS transistor N3 is coupled between the even bit line BLE and the first detection node SO1. The fourth NMOS transistor N4 is coupled between the odd bit line BLO and the first detection node SO1.
An even selection signal SELBLE is supplied to the gate of the third NMOS transistor N3. An odd selection signal SELBLO is supplied to the gate of the fourth NMOS transistor N4.
The fifth NMOS transistor N5 is coupled between the first and second detection nodes SO1, SO2. A detection signal SENSE is supplied to the gate of the fifth NMOS transistor N5.
The PMOS transistor P is coupled between a power source input terminal and the second detection node SO2. A precharge control signal PRECHSO_N is supplied to the gate of the PMOS transistor P.
In the nonvolatile memory device, when the intelligent verification operation is performed, a column scan method of performing fail verification for every four columns is used. Assuming that a bit line pair, including the even bit line BLE and the odd bit line BLO, is one column line, the memory cell array 110 includes a plurality of the column lines. That is, one page buffer PB is coupled to one column line.
In the column scan method, “column scan” means to check program verification results stored in the main latches L2 of page buffers PB coupled to all the column lines for every four column lines in the order of column addresses.
Meanwhile, the nonvolatile memory device 100 uses a cache program operation in order to reduce the program time. The cache program operation is performed in such a manner that, since the cache latch L1 is not used during the time for which a program is performed in the main latch L2, the cache latch L1 receives data to be programmed into the memory cells of a next page in order to reduce the program time.
FIG. 2 is a diagram illustrating a program operation of the nonvolatile memory device 100.
Referring to FIG. 2, to inform the nonvolatile memory device 100 of a program operation, a program command 80h is inputted to the nonvolatile memory device 100, and an address ADD, data DATA to be programmed, and an execution command 15h are also inputted to the nonvolatile memory device 100.
A program for an Nth page is performed in response to the command. The program operation of the nonvolatile memory device has already been known, and a detailed description thereof is omitted.
When the memory cells of the nonvolatile memory device 100 are multi-level cells (MLC) capable of storing 2 bits of data in each cell, the threshold voltages of the memory cells are shifted through the program operation so that they are included in first to fourth threshold voltage distributions. Next, program verification for the memory cells is performed using first to third verification voltages PV1 to PV3.
In general, when a program verification result using the first verification voltage PV1 is a program pass, the cache latch L1 is changed to an unused state. Here, the cache program operation of previously receiving data to be programmed into the memory cells of a next page can be performed.
That is, as shown in FIG. 2, when the program verification result using the first verification voltage PV1 is a program pass, the cache latch L1 is in an empty state (i.e., an unused state). Accordingly, during the time for which the program for the Nth page is performed until program verification results using the second and third verification voltages PV2, PV3 (not shown) indicate a program pass, a program command 80h, an address ADD, data DATA to be programmed, and an execution command 15h can be inputted to the nonvolatile memory device 100 in order to perform a program for an (N+1)th page.
The data to be programmed into the memory cells of the (N+1)th page is inputted to the cache latch L1. When the program for the Nth page is completed, the data inputted to the cache latch L1 and to be programmed into the (N+1)th page is moved to the main latch L2, and the program for the (N+1)th page is then performed.
However, when the nonvolatile memory device 100 performs the intelligent verification operation, the following problem can arise. Although the program verification result using the first verification voltage PV1 is a program pass, the program verification operations using the second and third verification voltages PV2, PV3 continue. At this time, when the intelligent verification operation is used, after verification data stored in the main latch L2 is moved to the cache latch L1, a verification operation using the column scan method must be simultaneously performed.
If, during the time for which the column scan for the intelligent verification operation is performed, the data to be programmed into the memory cells of the (N+1)th page is inputted to the cache latch L1, the two pieces of data are inputted to the cache latch L1. This leads to an error resulting from a collision between the data. To prevent such error, during the time for which the data for the (N+1)th page is inputted, the column scan is stopped (<Stop Column Scan>) until the input of data for the (N+1)th page is completed.
After the input of data for the (N+1)th page is completed, the data stored in the cache latch L1 is moved to a temporary latch (not shown). The column scan is then performed or resumed. Accordingly, the program time is increased.